It is inevitable to mount a memory device in fabricating a semiconductor device. A yield of the memory device affects a yield of the semiconductor device. The yield of the memory device cannot be ignored, in particular, in a semiconductor device to which a mass storage memory device is mounted and a semiconductor device to which a large quantity of memory devices is mounted.
In a memory device mounted to a semiconductor device, a redundancy memory cell is prepared in advance and a defective memory cell is switched to the redundancy memory cell, whereby a yield is improved. In order to switch the defective memory cell, it is necessary to give a memory device information for switching the defective memory cell to the redundancy memory cell. Thus, a fuse ROM is mounted to a semiconductor device in advance and a fuse of the fuse ROM is cut off as information of a position of the defective memory cell. A selector switches the defective memory cell to the redundancy memory cell in correspondence with a signal from the fuse ROM, reducing a defect ratio, so that improvement of the yield becomes possible.
Further, there is known a semiconductor integrated circuit device that has: a plurality of memory macros which an address is each allotted to, data of a defect address of a semiconductor memory is each transmitted to, stores the data of defect address, and can perform replacement with a redundancy cell; a plurality of nonvolatile storage elements which are provided by the number smaller than a number of the plurality of memory macros and store redundancy data to be transferred to the plurality of memory macros and address data indicating transfer destinations of the redundancy data in pair; and a transfer control circuit performing transfer of the redundancy data from the plurality of nonvolatile storage elements to the corresponding memory macros in accordance with the transfer destination address data (for example, see Patent Literature 1).
Further, there is known a semiconductor memory device that has: a memory cell array which includes a regular memory array part and a spare array part provided adjacently to the regular memory array part in order to replace a defective portion in the regular memory array; and a plurality of internal data lines for transmitting data to be inputted/outputted to/from the memory cell array part (for example, see Patent Literature 2).
Further, there is known a semiconductor integrated circuit device that has: a memory cell array in which a plurality of memory cells are disposed in an array; a redundancy circuit having a plurality of spare memory cells and replacing a defective memory cell in the memory cell array with the specific spare memory cell based on programmed address information; a storage circuit for programming address information and having a plurality of nonvolatile storage elements; and transferring circuit transferring the address information programmed in the storage circuit to the redundancy circuit (for example, see Patent Literature 3).
Further, there is known a semiconductor storage device that has: a clock generating circuit which includes a memory macro and a fuse box in which fuse data to be transferred to the memory macro is stored in a nonvolatile storage element, the fuse box generating a data transfer clock; a plurality of first fuse data latch circuits latching fuse data and transferring the fuse data serially on receiving a transfer clock; and a clock counter counting the transfer clock and generating a count up signal by a predetermined number of counts (for example, see Patent Literature 4).    [Patent Literature 1] Japanese Laid-open Patent Publication No. 2007-193879    [Patent Literature 2] Japanese Laid-open Patent Publication No. 2001-256794    [Patent Literature 3] Japanese Laid-open Patent Publication No. 2004-133970    [Patent Literature 4] Japanese Laid-open patent Publication No. 2007-311007